Digital I

Spring 2009

ECE 09.241

Rowan University

College of Engineering
Electrical & Computer Engineering

Instructor: Dr. Linda M. Head Room 334 Henry M. Rowan Hall 201 Mullica Hill Road, Glassboro, NJ 08028	(856) 256-5335 OFFICE (856) 256-5241 FAX head@rowan.edu
Meeting times: Class: TR 8:25am to 9:15am – RH104 Lab: F 8:00pm to 10:40pm – RH204/206 Text: Advanced Digital Design with the Verilog HDL by Michael D. Ciletti Syllabus

WORKSHEETS & PPT’s	READING ASSIGNMENTS	LINKS
WS1 WS2 WS3 WS4 WS5	Chapter 1 – all	Boolean Algebra Operator Precedence
WS6 WS7 WS8 WS9 WS10	Chapter 2 – 2.1 thru 2.4	Answers for WS10
Verilog1 WS11 WS12 WS14	Chapter 4 – 4.1 thru 4.2.6	Citing Sources
WS15 WS16 WS18	Chapter 3 - all	TEST 1 TOPICS
		Evaluating an SR Latch
		Timing Diagram
		SR Latch – HOLD case evaluation
LAB ASSIGNMENTS	HOMEWORK
LAB1 LAB2 LAB3	1 paragraph on Gray Codes	Spring Break Homework Answers
LAB4 LAB5	Truth table for NAND gate 2-input MUX circuit	TEST 2 TOPICS
	Spring Break Homework Assignment
	Homework due 3/31
	EXAMPLE HOMEWORK FORMAT
Spartan 3 Starter Kit Board Users Guide

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