Project 1: Prototype an FPGA-based Transmission Control Protocol (TCP) Stack

High-speed networks impose heavy processing demands on servers and storage devices, sharply limiting host CPU performance, system bandwidth, and scalability. Offloading TCP/IP processing into an embedded device is emerging as a solution to this dilemma. This project, as an initial stage of an on-chip TCP/IP offload engine, not only exposes students to object-oriented Hardware Definition Language (HDL) design techniques but also enhances student understanding and learning in computer networks. Four experiments are developed for this project.

• Lab 1: DESIGN A SYNCHRONOUS UP COUNTER WITH VARIANT COUNTING INCREMENTS
• Lab 2: DESIGN A FIRST IN FIRST OUT (FIFO) MEMORY
• Lab 3: DESIGN A NETWORK CLIENT THAT SUPPORTS A STOP -AND- WAIT RELIABLE TRANSMISSION PROTOCAL (TCP)
• Lab 4: ASSERTION AND VERIFICATION OF A FIFO DESIGN